Voltage regulators are an increasingly more important and vital component in today's power sensitive electronic systems. Specifically, mobile systems (e.g., in smart phones, tablets, etc.) relying on a finite power source (e.g., battery) might have a dozen or more voltage regulators that provide a targeted power supply level to each subsystem such that the power consumption of the overall system is optimized. Further, high speed data communication systems (e.g., 100 Gigabit Ethernet) might also implement voltage regulators that exhibit a wide bandwidth and high power supply rejection (PSR) to not only manage power consumption, but also to block or “reject” power supply voltage variations (e.g., switching noise from one or more system switching regulators) from the data signals on the data receive channels.
More specifically, such high speed data communication systems might deploy one or more low dropout (LDO) voltage regulators that exhibit a high PSR performance in a frequency range of 100 kHz to 100 MHz. Legacy LDO voltage regulator designs approach a high PSR in this range by implementing a high gain and high bandwidth front end operational amplifier (e.g., error amplifier). However, this technique increases the power consumption and noise of the LDO voltage regulator. Further, such techniques require a large amount of decoupling capacitance at the LDO voltage regulator output to suppress the peak PSR, adding costly die area to the design.
Techniques are needed to address the problem of implementing a wideband low dropout voltage regulator that exhibits high power supply rejection, and low power and low die area consumption, enabling the advancement of high speed data communication systems and other electronic systems.
None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed techniques for a wideband low dropout voltage regulator with power supply rejection boost. Therefore, there is a need for improvements.